1. Technical Field
Various embodiments of the invention relate generally to printed circuit board technology, and in particular relate to printed circuit boards with conductive inner layers.
2. Description of the Related Art
A typical printed circuit board (PCB) may have multiple signal routing layers containing traces to transmit signals to and from components mounted on the PCB. The PCB may also have a number of plated-through holes, or vias, used to connect specific traces on different signal routing layers. The vias may extend through one or more conductive layers (e.g., power and/or ground planes) between the signal routing layers. To prevent an inadvertent short circuit between a via and a conductive layer, a clearance hole (also called an anti-pad) within which the conductive material is removed is typically formed in the conductive layer around each via.
For example, a clearance hole having a larger diameter than the via may be formed in the conductive layers prior to drilling the via hole. Subsequently, the via hole may be drilled through the clearance hole and plated with a conductive plating material. If everything is done with sufficient precision, the smaller-diameter via will be centered within the larger-diameter clearance hole, and the difference in their respective diameters will prevent inadvertent electrical contact between the plated-through via and the conductive layer. However, laminate shift and/or drill mis-registration may cause the drill pattern to shift until part of the drilled via hole contacts the conductive material, which may result in an electrical short circuit between the conductive area outside the clearance hole and the conductive plating material in the via.
To reduce the probability of electrical shorts between vias and conductive layers due to drilling errors, PCB manufacturers typically require a minimum distance between a drilled via hole and the inner edge of a clearance hole, thus increasing the minimum allowed size of the clearance hole. Also, design rules may require that conductive traces carrying controlled impedance signals are not routed over a clearance hole on an adjacent conductive plane used as a reference in order to avoid fluctuations in the impedance caused by a discontinuity in the critical dielectric spacing. For these reasons, increasing the size of the clearance hole to accommodate possible drill mis-registration in the via hole may reduce the amount of usable area on signal routing layers above and/or below the conductive layers.